One of the most critical reliabilitY problems afflicting silicon integrated circuits (IC) area voids which develop in the narrow (&lt;10 .mu.m) aluminum metallization deposited on the surface to provide interconnecting conductors. These voids occur at the edge of a conductor, and can extend across the entire width of the conductor causing an open circuit failure condition. When the void occurs only part way across, there was concern that it could lead to a time-dependent failure when the chip is electrically functional. Another concern was thought to be that residual stresses in the aluminum metallization conductor could cause further time-dependent propagation of the voids even when not electrically operational.
Silicon ICs fabricated for spacecraft applications were found to have voids in the aluminum metallization during a routine destructive physical inspection. The ICs had already been burned in and flight qualified, and had completed a final reliability evaluation by means of a life test for 1300 house at 125.degree. C. Following the life test, the parts were found to be electrically functional with no problems of any kind indicated until "delidding" for visual inspection. Voids were found during that visual inspection using a scanning electron microscope (SEM). When equivalent IC chips yet to be lidded were inspected, no voids were found. Consequently, the source of the voids was believed to be caused by the process of heat-sealing the lids onto the ceramic packages rather than any of the follow-on testing processes.
A review of the literature revealed that such voids in aluminum metallization of IC chips is observed throughout the microelectronics industry and were believed to occur during the IC wafer process, die-attach process, and also during the lidding process. These voids being observed were different from those created by electromigration effects at high current densities (.gtoreq.500,000 amps/cm.sup.2) in that these ICs were unbiased up until the time the voids were observed, and were sometimes observed in places where current would never flow even if biased. Such voids induced without electrical current have been referred to in the literature as "stress-induced voids."
The aluminum metallization conductors on the ICs fabricated for spacecraft applications were 1 micron thick and 7 microns wide and the voids observed on the edges of the lines and extended inwards approximately 0.6 to 2.0 microns. These lines carry a peak amperage of about 100.mu. amps, and based on the 500,000 amp/cm.sup.2 criteria, would not be a reliability concern in respect to electromigration. However, the concern that evolved was related to the possibility of further void propagation during a long-term mission lifetime (80,000 hours at 35.degree. C.), which could conceivably narrow the aluminum metallization lines to increase current at the void above 500,000 amp/cm.sup.2, and thus cause electromigration effects leading to open circuit failures (cracks).
No literature has been found which specifically address the issue of slow. long-term (i.e., 80,000 hours) void propagation at nominally constant ambient temperature. It was noted, however, that virtually all theoretical efforts at modeling these voids tended to consider stresses in the aluminum metallization conductors resulting from thermal expansion mismatches with the silicon substrates and the glass passivation over the metallization. These stresses were related in turn to creep of the aluminum metallization lines, vacancy migrations within the aluminum and resultant formation of void clusters and other metallurgical characteristics.
In apparent support of stress considerations based on thermal expansion mismatch effects, these same ICs had experienced voids in earlier efforts to use a high temperature (.about.460.degree. C.) gold eutectic as the die-attach. When the die-attach process was switched to an epoxy which cures under 200.degree. C., void problems ceased to occur. Further, two vendors had been involved in packaging these ICs, and there were differences between them in the peak die temperatures reached during the lid sealing process. The peak temperatures for vendor "A" was equal to or less than 240.degree. C., whereas for vendor "B", the peak die temperatures reached a range between 280.degree. C. to 330.degree. C. Vendor "B" was lidding the ICs for spacecraft applications when the voids were discovered by the routine destructive physical analysis referred to above. No voids were found in ICs lidded by vendor "A" at the lower die temperatures under 240.degree. C.
It was postulated that the voids were due in part to thermal-expansion mismatches associated with the higher levels of stresses (strains) which would be developed in the aluminum metallization conductors, resulting from the greater temperature differences between ambient and either the die temperatures of vendor "B", or the gold eutectic bonding temperatures. An experiment was undertaken to expose the ICs with voids to a series of lower temperatures below ambient to see if a further increase in the voids would occur from added stresses and strains associated with the greater temperature differences. The intent was to monitor the propagation of the voids as a function of time and temperature to develop a mathematical relationship which could be used for life time extrapolations at ambient operating temperatures.
In preparation for this experiment, a preliminary extreme temperature test (direct immersion into liquid nitrogen from ambient) was carried out to achieve an appreciation of the magnitude of further void growth. Unexplainably, there was no detectable void growth. In fact, nothing had happened at all. This unexpected result prompted a second extreme temperature test which involved heating the parts first to 200.degree. C. for 30 minutes followed by direct immersion into liquid nitrogen (-196.degree. C.). It was surprisingly observed that the voids did not experience any growth, and instead had been healed by this extreme thermal treatment. The voids were gone, and the aluminum metallization conductors were fully restored.
These preliminary tests were all carried out with the glass passivation over the surface of the ICs remaining intact. The ability to observe the voids through the glass passivation was made possible by an enhanced SEM backscattering technique. SEM photographs of a typical void pattern viewed through the glass passivation by enhanced backscattering and by normal SEM with the glass passivation removed were virtually identical. This demonstrated that removal of the glass passivation did not produce voids.
A controlled experiment was carried out in which unlidded parts without voids were exposed for 30 minutes to temperatures of 200.degree., 250.degree., 300.degree., 350.degree., and 400.degree. C. Following the exposure time, half of the parts from each temperature were rapidly cooled by direct immersion into liquid nitrogen, while the other half were slowly cooled to ambient over a 2-4 hours time period. Observations of voids in the ICs are detailed in the following table;
TABLE I ______________________________________ Effect of High Temperature Exposure and Cooling (Annealing) Rate on Void Formation Peak Cooling (Annealing) Rate Conditions Exposure Direct Immersion 2-4 Hours Slow Temperature* into Liquid Nitrogen Cooling to Ambient** .degree.C. Voids Voids Void Density ______________________________________ 200 None None 0 250 None 2 3 300 None 15 25 350 None 40 69 400 None 80 138 ______________________________________ *Parts heated at indicated temperature for 30 minutes. **Number of voids counted over a line length of 0.580mm (22.8 mils). The void density if reported as voids/mm.
For all parts rapidly cooled from a high temperature between 200.degree.and 400.degree. C. by direct immersion into liquid nitrogen, no voids were formed. In contrast, the slow-cooled ICs developed voids, with the void density increasing with increasing temperature above 200.degree.C.
The heating and cooling pattern on these ICs were then exchanged. All of the ICs without voids were reheated for 30 minutes at 300.degree. C. followed by slow cooling to ambient over a 2-4 hours time period. They now all had voids. Conversely, all of the parts with voids were reheated at 200.degree. C. for 30 minutes followed by direct immersion into liquid nitrogen. Interestingly, the voids did not heal. However, the test was repeated on these ICs having voids at progressively higher exposure temperatures. When heated finally at 350.degree. C. or higher for 30 minutes followed by direct immersion into liquid nitrogen, the voids were all healed. Thus, the process of void formation and healing has been found to be reversible for the silicon ICs.
It is unclear why voids produced during the lid-sealing process at vendor "B" could be healed by liquid nitrogen quenching from temperature exposures as low as 200.degree. C., in contrast to this controlled experiment. One explanation may be that the exposure time of heating during the lid-sealing process of vendor "B" is in the order of 1 minute, compared to 30 minutes used in the control experiment.
Coincidentally, vendor "A" bad separately fabricated other devices using narrower aluminum metallization conductors (.about.3 to 4 microns wide) which were severely full of voids and rejected for that reason. With the discovery of a thermal treatment in the controlled experiment just described above, this same healing treatment was carried out for these other defective devices. However, using a 200.degree. C. peak temperature, that treatment did not heal the voids. Again it was reasoned that perhaps a higher peak temperature was needed, such as a peak temperature of 400.degree. C. which healed the voids when used, although some partial healing was observed to start at temperatures above 300.degree. C. for these other defective devices.
The void densities in the V.sub.DD and V.sub.SS metallization conductors of the ICs used in the controlled experiment were measured on ICs from different production lots after burn-in as part of the initial void propagation investigation. The intent was to experimentally find production lots which may be generically free of voids. The results of 29 lots are given in the following Table II in units of voids/mm.
TABLE II ______________________________________ Void Densities Measured in ICs After Burn-In Void Density Voids/mm Lot No. V.sub.DD V.sub.SS ______________________________________ 1 39.2 28.6 2 45.7 17.1 3 36.6 20.2 4 48.2 32.6 5 66.9 43.0 6 67.8 49.7 7 60.2 40.0 8 50.7 30.5 9 77.9 59.0 10 71.0 84.8 11 46.7 71.0 12 0 3.43 13 28.4 36.6 14 30.3 30.8 15 40.6 29.1 16 40.9 44.2 17 21.1 19.4 18 7.97 12.1 19 15.5 38.5 20 45.6 64.5 21 0 8.13 22 47.8 48.4 23 48.3 50.6 24 57.3 58.1 25 18.4 24.0 26 0 0 27 11.4 14.5 28 0 0 29 13.8 20.9 ______________________________________
Note that the values range from 0 to 84 but tend to cluster in the range of 40 to 60 voids/mm. These values in Table II can be compared with the values reported in Table I for the controlled experiment, which reveals a relationship between void density and the peak exposure temperature. The peak die temperature during the lid-sealing process at vendor "B" ranged between 280.degree. to 330.degree. C., which predicts from Table I void densities nominally in the range of 3 to near 69 voids/mm. These values are consistent with those given in Table II from actual production lots. It can be inferred that these voids are thermally driven with the void density related to lid-sealing temperatures in effect at the time each lot of parts was being processed.
This same activity which counted void densities in the production lots after burn-in also involved measurement of the length of the voids included in the count, a total of 1584 measurement. The void lengths ranged between 0.6 to 2.0 microns, and the data was statistically analyzed and found to follow a log-normal distribution. This made it possible to predict probabilities for the possibilities of large void lengths in parts still lidded. The predictions are given in the following Table III, which indicates the probability of having a void length greater than 2 microns was in the order of 0.3%.
TABLE III ______________________________________ Void-Length Distribution in IC's Probability of Void-Length &gt; L L, Length (Microns) After Burn-In* After Life-Test** ______________________________________ 2 .003098 .005760 3 .000075 .000060 4 .000003 .00000089 5 .00000018 Essentially Zero 6 Essentially Zero Essentially Zero ______________________________________ *Based on 1584 void length measurements. **Based on 119 void length measurements.
The probability falls off rapidly with increasing void length and becomes virtually zero at 6 microns. Using this statistical analysis technique offered a possibility to investigate if voids can propagate from thermal aging. The parts which were delidded for the routine destructive parts analysis following the life-test at 125.degree. C. for 1300 hours had a total of 119 voids, whose lengths were measured. Again, the void-lengths ranged between 0.6 to 2.0 microns, and followed a log-normal distribution. The probabilities versus void-length for the data measured after the life test are reported in Table III and can be compared with the burn-in data. There is virtually no difference, and certainly there are no indications of any substantial void growth from thermal aging for 1300 hours at 125.degree. C. for these ICs.